Recently, Marvell, an American IC design company, officially released the data center chip based on TSMC 3nm, which is also the first 3nm data infrastructure chip in the industry.

According to TSMC's previous introduction, compared to the 5nm process, the logic density of the 3nm process will increase by about 70%, with a speed increase of 10-15% at the same power consumption, or a power reduction of 25-30% at the same speed.

TSMC's 3-nanometer chip can be used for new product design, including basic IP building blocks, 112G XSR SerDes (serializer/deserializer), Long Reach SerDes, PCIe Gen 6 PHY/CXL 3.0 SerDes, and 240 Tbps parallel chip to chip interconnection.

According to Marvell, SerDes and parallel interconnects serve as high-speed channels for exchanging data between chiplets or silicon components. Together with 2.5D and 3D packaging, these technologies will eliminate system level bottlenecks to drive the most complex semiconductor designs. In addition, as ultra large data center racks may contain tens of thousands of SerDes links, SerDes can also help reduce pin, wiring, and circuit board space, reducing costs.

Official data shows that the new parallel chip to chip interconnection can achieve aggregated data transmission of up to 240Tbps, which is 45% faster than available alternatives for multi chip packaging. In other words, the interconnection transmission rate is equivalent to downloading ten thousand high-definition movies per second, even though the distance is only a few millimeters or less.

Marvell integrates SerDes and interconnect technology into its flagship silicon solutions, including Teralynx switches, PAM4 and coherent DSP, Alaska Ethernet Physical Layer (PHY) devices, OCTEON processors, Bravera storage controllers, Brightlane automotive Ethernet chipsets, and customized ASICs. Turning to 3 nanometers can reduce the cost and power consumption of chips and computing systems while maintaining signal integrity and performance.