Two dimensional semiconductors are the new path that attracts the most attention in the development of integrated circuit technology to 1 nm nodes. Although the international industry believes that introducing two-dimensional semiconductors can effectively solve the problem of transistor size scaling in CMOS planar processes, one of its important development bottlenecks is the need to provide high-quality and rapidly produced large-scale wafers. So far, major leading companies in the world, such as Intel, Samsung, TSMC, and IMEC R&D centers in Europe, have invested significant resources in two-dimensional semiconductors and actively introduced international leading teams. Currently, researchers have developed various strategies to prepare large-area two-dimensional semiconductors, among which chemical vapor deposition (CVD) is a widely promising technology. However, the main research focuses more on laboratory level performance improvement and does not fully consider the scale and cost of material growth.

On September 29, 2023 Beijing time, the team led by Zhou Peng and Bao Wenzhong from Fudan University made significant research progress and invented a two-dimensional material growth method for integrated circuit manufacturing, which can achieve rapid growth of uniform and single-layer materials on mainstream 12 inch (300 mm) wafers in the industry, The relevant achievements were published in the top international journal Nature Materials under the title of "12-inch growth of uniform MoS2 monolayer for integrated circuit manufacturing". This work not only provides a new idea for the growth of two-dimensional materials by CVD, but also achieves a breakthrough from 0 to 1; At the same time, it also focuses on the integrated circuit applications of two-dimensional semiconductors, fully considering the collaborative optimization of scale cost performance (S-C-P) indicators, with a focus on the conversion from 1 to 10.

The difficulty of traditional two-dimensional material CVD growth lies in the precise controllability and batch repeatability at the atomic level, which requires collaborative optimization of many control parameters, including special treatment of the growth substrate. This achievement groundbreaking adopts the precursor design of sponge slow-release structure and the distribution of multiple sulfur sources optimized by fluid dynamics, thus achieving quasi-static growth of two-dimensional materials; At the same time, a special buffer layer is grown by atomic layer deposition on any substrate (including silicon), accurately controlling uniform single-layer nucleation, and finally obtaining a large-area two-dimensional semiconductor uniform growth technology. It is applicable to various two-dimensional semiconductors, and can quickly achieve full coverage of low defects in a two-dimensional single-layer within a 12 inch wafer in 15 minutes. Thanks to the ability to grow on any substrate, researchers have also demonstrated the wafer structure process of silicon on insulator (SOI) to produce transistor arrays, avoiding complex transfer methods. The two-dimensional material on insulator (2D OI) demonstrated in this achievement has atomic level semiconductor channels, which can fully leverage the advantages of two-dimensional semiconductors in advanced manufacturing processes. In addition, the material characterization results demonstrate that the grown two-dimensional thin film grains have good atomic level splicing, and the electrical performance of two-dimensional transistors at room temperature is not directly related to grain size or polycrystalline grain boundaries. The statistical results show excellent device electrical uniformity. These findings provide a transitional development path for two-dimensional semiconductors from the laboratory to the industry.